Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device

ABSTRACT

A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2003-121631, filed Apr.25, 2003, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integratedcircuit device and a system using the semiconductor integrated circuitdevice and, more particularly, is applied to a high-speed input/outputcircuit which transmits a pair of differential signals.

[0004] 2. Description of the Related Art

[0005] Recently, the speed of an input/output circuit (to be simplyreferred to as an I/O circuit) increases, and a semiconductor integratedcircuit device must process an input/output signal in the GHz band. Toprocess a signal of such high frequency by the I/O circuit, for example,a pair of differential signals resistant to noise are used for the inputand output. Alternatively, bump connection capable of implementing ashort, uniform wiring length is used for connection between an LSI and apackage.

[0006]FIG. 1 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals, in order toexplain a conventional semiconductor integrated circuit device. Adifferential output driver circuit 11 comprises differential inputMOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) 12 and 13,load elements 14 and 15, and a constant-current source 16. The gates ofthe differential input MOSFETs 12 and 13 receive a pair of differentialsignals from a circuit 17 on the input stage. The load elements 14 and15 are respectively connected between the drains of the differentialinput MOSFETs 12 and 13 and a power supply V_(DD). The sources of thedifferential input MOSFETs 12 and 13 are commonly connected, and theconstant-current source 16 is connected between the common source nodeand ground V_(SS).

[0007] One end of a global interconnection 18 is connected to the nodebetween the drain of the MOSFET 13 and the load element 15, and theother end is connected to a bump 20. One end of a global interconnection19 is connected to the node between the drain of the MOSFET 12 and theload element 14, and the other end is connected to a bump 21. The bumps20 and 21 function as IC or LSI output terminals and are formed on achip surface. Each of the bumps 20 and 21 is connected to one end of acorresponding one of transmission lines 22 and 23 formed within apackage (bonding wires, lead frame, TAB tape, or the like) or on aprinted circuit board on which the semiconductor integrated circuitdevice is mounted.

[0008] In a system LSI, many differential output driver circuits 11 arearranged at I/O portions. The transmission lines 22 and 23 areterminated by the same resistances as the characteristic impedances ofthe transmission lines 22 and 23 on the receiving side, which is notshown in FIG. 1.

[0009] If the differential output driver circuit 11 operates ideally,the circuit 11 is resistant to external noise. However, the followingproblems occur because of the presence of many I/O circuits within thechip.

[0010] (a) If the signal line lengths of a pair of differential signalsare not equal to each other, a skew in propagation delay time occurs atthe ends of the transmission lines 22 and 23.

[0011] (b) The skew generates an in-phase current between thetransmission lines 22 and 23 (ideally no in-phase current is generated),generating noise (common mode noise) which is radiated upon couplingwith a neighboring pattern.

[0012] Examples of the line length difference which causes problems (a)and (b) are as follows.

[0013] (1) The wiring length difference between the transmission lines22 and 23 formed within a package (bonding wire, lead frame, or TABtape) or on a printed circuit board.

[0014] (2) The wiring length difference between the globalinterconnections 18 and 19 which respectively connect the load elements14 and 15 and the bumps 20 and 21.

[0015] As for difference (1), the wiring lengths are often adjusted bybending one wire into a U shape on the printed circuit board so as tomake the wiring lengths equal to each other. If the frequency of a pairof differential signals increases to the GHz band, the U-shaped wireundesirably radiates electromagnetic waves. As the number of I/Oportions increases, many U-shaped wires must be arranged on the printedcircuit board, increasing the transmission line layout area.

[0016] As for difference (2), the wiring lengths are adjusted on the LSIsimilarly to difference (1). Adjustment of the lengths of a pair ofdifferential lines on the LSI for all I/O portions wastes the space. Thereturn current from ground suffers a path difference depending on thepositional relationship between a bump serving as a ground terminal andthe signal input/output bumps 20 and 21. A skew equal to or larger thanthe line length difference between the global interconnections 18 and 19may occur. At a GHz-band frequency, the wiring length difference betweenthe global interconnections 18 and 19 may generate a skew or common modenoise.

[0017] As described above, to reduce a skew or common mode noise, theline lengths of a pair of the differential lines must be kept as equalto each other as possible. In practice, the line length differencebetween a pair of differential lines cannot be eliminated owing tovariations caused by the manufacturing tolerance of the package orprinted circuit board.

[0018] Especially when a pair of differential signals have a GHz-bandfrequency, such variations greatly influence the transmissioncharacteristic. In mass production, a system having a function ofchecking a margin for manufacturing variations is required.

[0019] For example, Japanese Patent No. 3,144,199 discloses a skewcorrection circuit using a differential amplifier and resistor. If theskew correction circuit is arranged at each I/O portion, the areaoccupied on the chip greatly increases due to a large circuit scale.Application of the skew correction circuit to a semiconductor integratedcircuit device which processes a signal of a high GHz-band frequency isnot practical.

[0020] In this manner, the conventional semiconductor integrated circuitdevice generates a skew or common mode noise by the line lengthdifference between a pair of differential lines.

[0021] In mass production, a system using a semiconductor integratedcircuit device capable of checking a margin for manufacturing variationsis required.

BRIEF SUMMARY OF THE INVENTION

[0022] According to one aspect of the present invention, there isprovided a semiconductor integrated circuit device comprising a chip onwhich an integrated circuit is formed, a differential output drivercircuit which externally outputs a pair of differential signalsgenerated by the integrated circuit, first and second signal lines whichtransmit the pair of differential signals output from the differentialoutput driver circuit, and a delay unit which is connected in the chipto at least one of the first and second signal lines, has an activeelement for delaying signals passing through the first and second signallines so as to make delays of the signals substantially equal to eachother, and compensates for a signal delay time generated by a linelength difference between the first and second signal lines.

[0023] According to another aspect of the present invention, there isprovided a semiconductor integrated circuit device comprising a chip onwhich an integrated circuit is formed, a differential output drivercircuit which externally outputs a pair of differential signalsgenerated by the integrated circuit, first and second signal lines whichtransmit the pair of differential signals output from the differentialoutput driver circuit, and a delay unit which is connected in the chipto at least one of third and fourth signal lines which transmit the pairof differential signals from the integrated circuit to the differentialoutput driver circuit, has an active element for delaying at least oneof the pair of differential signals so as to make delays of the signalspassing through the first and second signal lines substantially equal toeach other, and compensates for a signal delay time generated by a linelength difference between the first and second signal lines.

[0024] According to still another aspect of the present invention, thereis provided a system using a semiconductor integrated circuit device,comprising a semiconductor integrated circuit device comprising adifferential output driver circuit which externally outputs via firstand second signal lines a pair of differential signals generated withina chip, a first receiving unit which receives the pair of differentialsignals output from the semiconductor integrated circuit device via thefirst and second signal lines, a signal processing unit which processesthe pair of differential signals received by the first receiving unitand generates correction data for correcting unbalance between the pairof differential signals, a transmitting unit which transmits thecorrection data generated by the signal processing unit to thesemiconductor integrated circuit device, a second receiving unit whichis arranged in the semiconductor integrated circuit device and receivesthe correction data transmitted from the transmitting unit, and a delayunit which changes a delay time on the basis of the correction datareceived by the second receiving unit, has an active element fordelaying signals passing through the first and second signal lines so asto make delays of the signals substantially equal to each other, andcompensates for a signal delay time generated by a line lengthdifference between the first and second signal lines.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0025]FIG. 1 is a circuit diagram showing an output circuit whichtransmits a pair of differential signals, in order to explain aconventional semiconductor integrated circuit device;

[0026]FIG. 2 is a circuit diagram showing an output circuit whichtransmits a pair of differential signals, in order to explain asemiconductor integrated circuit device according to the firstembodiment of the present invention;

[0027]FIG. 3 is a circuit diagram showing a concrete implementationexample (Example 1) of a delay element in the semiconductor integratedcircuit device according to the first embodiment;

[0028]FIG. 4 is a circuit diagram showing another concreteimplementation example (Example 2) of the delay element in thesemiconductor integrated circuit device according to the firstembodiment;

[0029]FIG. 5 is a circuit diagram showing still another concreteimplementation example (Example 3) of the delay element in thesemiconductor integrated circuit device according to the firstembodiment;

[0030]FIG. 6 is a circuit diagram showing still another concreteimplementation example (Example 4) of a delay element in thesemiconductor integrated circuit device according to the firstembodiment;

[0031]FIG. 7 is a circuit diagram showing an output circuit whichtransmits a pair of differential signals, in order to explain asemiconductor integrated circuit device according to the firstembodiment of the present invention;

[0032]FIG. 8A is a diagram showing the peak-to-peak value of thewaveforms of a pair of differential signals in a common mode as theresults of simulating the effect of inserting a delay element on theinput stage of a differential line;

[0033]FIG. 8B is a diagram showing the maximum value of the waveforms ofa pair of differential signals in a differential mode as the results ofsimulating the effect of inserting the delay element on the input stageof the differential line;

[0034]FIG. 8C is a waveform chart showing transition a pair ofdifferential signals;

[0035]FIG. 9 is a circuit diagram showing a concrete implementationexample (Example 5) of a delay element in the semiconductor integratedcircuit device according to the second embodiment of the presentinvention;

[0036]FIG. 10 is a circuit diagram showing another concreteimplementation example (Example 6) of the delay element in thesemiconductor integrated circuit device according to the secondembodiment of the present invention;

[0037]FIG. 11 is a circuit diagram showing still another concreteimplementation example (Example 7) of the delay element in thesemiconductor integrated circuit device according to the secondembodiment of the present invention;

[0038]FIG. 12 is a circuit diagram showing still another concreteimplementation example (Example 8) of the delay element in thesemiconductor integrated circuit device according to the secondembodiment of the present invention;

[0039]FIG. 13 is a circuit diagram showing still another concreteimplementation example (Example 9) of the delay element in thesemiconductor integrated circuit device according to the secondembodiment of the present invention;

[0040]FIG. 14 is a circuit diagram for explaining a semiconductorintegrated circuit device according to the third embodiment of thepresent invention;

[0041]FIG. 15 is a circuit diagram for explaining a semiconductorintegrated circuit device and a system using the semiconductorintegrated circuit device according to the fourth embodiment of thepresent invention;

[0042]FIG. 16 is a circuit diagram for explaining a semiconductorintegrated circuit device and a system using the semiconductorintegrated circuit device according to the fifth embodiment of thepresent invention; and

[0043]FIG. 17 is a circuit diagram for explaining a semiconductorintegrated circuit device and a system using the semiconductorintegrated circuit device according to the sixth embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION FIRST EMBODIMENTS

[0044]FIG. 2 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals, in order toexplain a semiconductor integrated circuit device according to the firstembodiment of the present invention. Similar to the circuit shown inFIG. 1, a differential output driver circuit 31 comprises differentialinput MOSFETs 32 and 33, load elements 34 and 35 such as resistors, anda constant-current source 36. The gates of the differential inputMOSFETs 32 and 33 receive a pair of differential signals from a circuit(integrated circuit) 37 on the input stage. The load elements 34 and 35are respectively connected between the drains of the differential inputMOSFETs 32 and 33 and a power supply V_(DD). The sources of thedifferential input MOSFETs 32 and 33 are commonly connected, and theconstant-current source 36 is connected between the common source nodeand ground V_(SS).

[0045] One end of a global interconnection 38 is connected via a delayelement (DELAY) 44 to the node between the drain of the MOSFET 33 andthe load element 35, and the other end is connected to a bump 40. Oneend of a global interconnection 39 is connected to the node between thedrain of the MOSFET 32 and the load element 34, and the other end isconnected to a bump 41.

[0046] The bumps 40 and 41 function as IC or LSI output terminals andare formed on a chip surface. Each of the bumps 40 and 41 is connectedto one end of a corresponding one of transmission lines 42 and 43 formedwithin a package (bonding wires, lead frame, TAB tape, or the like) oron a printed circuit board on which the semiconductor integrated circuitdevice is mounted.

[0047] The delay element 44 adjusts the signal delay time generated bythe line length difference between a pair of differential lines to besubstantially equal to each other. For example, when a signal line(indicated by a broken arrow SA) formed by the global interconnection38, bump 40, and transmission line 42 is shorter by ΔL than a signalline (indicated by a broken arrow SB) formed by the globalinterconnection 39, bump 41, and transmission line 43, the delay element44 delays a signal on the signal line SA so as to make the delays ofsignals on the signal lines SA and SB substantially equal to each other.The signal delay amount by the delay element 44 may be fixed or changed.

[0048] In a system LSI, many differential output driver circuits 31 arearranged at I/O portions. The transmission lines 42 and 43 areterminated by the same resistances as the characteristic impedances ofthe transmission lines 42 and 43 on the receiving side, which is notshown in FIG. 2.

[0049] In this arrangement, the delay element 44 can compensate for thesignal delay time generated by the line length difference between a pairof differential lines, reducing a skew and common mode noise.

EXAMPLE 1

[0050]FIG. 3 shows a concrete implementation example of the delayelement 44 in the semiconductor integrated circuit device according tothe first embodiment. In FIG. 3, the same reference numerals as in FIG.2 denote the same parts, and a detailed description thereof will beomitted.

[0051] In this example, a capacitance element 44A formed from the gatecapacitance of an active element is arranged as the delay element 44shown in FIG. 2.

[0052] For example, in a MOS capacitor, a very thin oxide film serves asa capacitor dielectric, and the line length difference (delay timedifference) between a pair of differential lines (signal lines SA andSB) can be compensated for by a very small pattern occupation area. TheMOS capacitor can be formed simultaneously in the step of forming thedifferential input MOSFETs 32 and 33. No new manufacturing step need beadded for forming the delay element 44.

[0053] In this arrangement, the capacitance element 44A can compensatefor the signal delay time generated by the line length differencebetween a pair of differential lines, reducing a skew and common modenoise.

EXAMPLE 2

[0054]FIG. 4 shows another concrete implementation example of the delayelement 44 in the semiconductor integrated circuit device according tothe first embodiment. In FIG. 4, the same reference numerals as in FIG.2 denote the same parts, and a detailed description thereof will beomitted.

[0055] In this example, a control circuit 45A and a plurality of (n)capacitance elements (e.g., MOS capacitors) 44A-1, . . . , 44A-n eachformed from the gate capacitance of an active element are arranged asthe delay element 44 shown in FIG. 2. The control circuit 45A isinterposed between one electrode of each of the capacitance elements44A-1, . . . , 44A-n and one end of the global interconnection 38. Thecontrol circuit 45A controls a potential applied to one electrode ofeach of the capacitance elements 44A-1, . . . , 44A-n, selectivelychanging the thickness of the depletion layer of each capacitanceelement. The capacitance connected to one end of the globalinterconnection 38 can be changed to freely set the signal delay amount.

[0056] This arrangement can finely control the signal delay amount byusing the control circuit 45A, in addition to the effects of Example 1.

[0057] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

[0058] The capacitance ratio of the n capacitance elements 44A-1, . . ., 44A-n is set to 1:2:4: . . . : 2_(n) so as to change the delay amountat a 2^(n)-power step. By selecting the capacitance elements 44A-1, . .. , 44A-n, the delay amount can be set at a fine step within a widerange of a large capacity to a small capacity, and can be moreaccurately controlled.

EXAMPLE 3

[0059]FIG. 5 shows still another concrete implementation example of thedelay element 44 in the semiconductor integrated circuit deviceaccording to the first embodiment. In FIG. 5, the same referencenumerals as in FIG. 2 denote the same parts, and a detailed descriptionthereof will be omitted.

[0060] In this example, the current path of each of switching elements(MOSFETs) 46-1, . . . , 46-n is connected between one electrode (gateelectrode) of a corresponding one of capacitance elements 44A-1, . . . ,44A-n and one end of the global interconnection 38. A control circuit45B selectively applies a high-level (“H”-level) or low-level(“L”-level) potential to the gates of the MOSFETs 46-1, . . . , 46-n,and controls their ON/OFF operation.

[0061] Which gate capacitance (capacitance element 44A-1, . . . , 44A-n)is to be connected to the global inter-connection 38 can be selected,and the signal delay amount can be freely controlled.

[0062] The capacitance ratio of the n capacitance elements 44A-1, . . ., 44A-n is set to 1:2:4: . . . : 2_(n) so as to change the delay amountat a 2n-power step. By selecting the capacitance elements 44A-1, . . . ,44A-n, the delay amount can be set at a fine step within a wide range ofa large capacity to a small capacity, and can be more accuratelycontrolled.

[0063] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

EXAMPLE 4

[0064]FIG. 6 shows still another concrete implementation example of thedelay element 44 in the semiconductor integrated circuit deviceaccording to the first embodiment. In FIG. 6, the same referencenumerals as in FIG. 2 denote the same parts, and a detailed descriptionthereof will be omitted.

[0065] In this example, one electrode (gate electrode) of each ofcapacitance elements 44A-1, . . . , 44-n is connected to one end of theglobal interconnection 38. A control circuit 45C selectively applies an“H”- or “L”-level potential to the other electrode (layer which forms acounter electrode with respect to the gate electrode) of each of thecapacitance elements 44A-1, . . . , 44A-n.

[0066] The capacitances of the capacitance elements 44A-1, . . . , 44A-nconnected to one end of the global interconnection 38 can be selected,freely controlling the signal delay amount.

[0067] In Example 4, similar to Examples 2 and 3, the capacitance ratioof the n capacitance elements is set to 1:2:4: . . . :2^(n) so as tochange the delay amount at a 2^(n)-power step. By selecting thecapacitance elements 44A-1, . . . , 44A-n, the delay amount can be setat a fine step within a wide range of a large capacity to a smallcapacity, and can be more accurately controlled.

[0068] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

[0069] In the first embodiment and Examples 1 to 4, the delay element 44is connected to only one having a shorter line length out of a pair ofglobal inter-connections 39 and 38. It is also possible to arrange thedelay elements 44 on both the global interconnections 38 and 39 andadjust signal delay times generated by the line length differencebetween a pair of differential lines so as to be substantially equal toeach other.

[0070] A plurality of delay elements having different structures may becombined and connected to at least one of a pair of globalinterconnections 38 and 39.

SECOND EMBODIMENT

[0071]FIG. 7 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals, in order toexplain a semiconductor integrated circuit device according to thesecond embodiment of the present invention. Similar to the circuit shownin FIG. 2, a differential output driver circuit 31 comprisesdifferential input MOSFETs 32 and 33, load elements 34 and 35, and aconstant-current source 36. The gate of the differential input MOSFET 33receives one of a pair of differential signals via a delay element(DELAY) 44 from a circuit (integrated circuit) 37 on the input stage.The gate of the differential input MOSFET 32 receives the otherdifferential signal from the circuit 37.

[0072] The load elements 34 and 35 such as resistors. are respectivelyconnected between the drains of the differential input MOSFETs 32 and 33and a power supply V_(DD). The sources of the differential input MOSFETs32 and 33 are commonly connected, and the constant-current source 36 isconnected between the common source node and ground V_(SS).

[0073] One end of a global interconnection 38 is connected to the nodebetween the drain of the MOSFET 33 and the load element 35, and theother end is connected to a bump 40. One end of a global interconnection39 is connected to the node between the drain of the MOSFET 32 and theload element 34, and the other end is connected to a bump 41.

[0074] The bumps 40 and 41 function as IC or LSI output terminals andare formed on a chip surface. Each of the bumps 40 and 41 is connectedto one end of a corresponding one of transmission lines 42 and 43 formedwithin a package or on a printed circuit board on which thesemiconductor integrated circuit device is mounted.

[0075] The delay element 44 adjusts the signal delay time generated bythe line length difference between a pair of differential lines to besubstantially equal to each other. For example, when a signal line(indicated by a broken arrow SA) formed by the global interconnection38, bump 40, and transmission line 42 is shorter by ΔL than a signalline (indicated by a broken arrow SB) formed by the globalinterconnection 39, bump 41, and transmission line 43, the delay element44 delays one of a pair of differential signals that is supplied fromthe circuit 37 to the gate of the MOSFET 33 via a signal line (indicatedby a broken arrow SC). Accordingly, a signal on the signal line SAcorresponding to the signal line SC is delayed, and the delays ofsignals on the signal lines SA and SB are adjusted to be substantiallyequal to each other. The signal delay amount by the delay element 44 maybe fixed or changed.

[0076] In a system LSI, many differential output driver circuits 31 arearranged at I/O portions. The transmission lines 42 and 43 areterminated by the same resistances as the characteristic impedances ofthe transmission lines 42 and 43 on the receiving side, which is notshown in FIG. 7.

[0077] In this embodiment, the delay element 44 is inserted into thesignal line SC on the input side of the differential output drivercircuit 31. The delay element 44 may be inserted in a signal line whichtransmits an arbitrary pair of differential signals in the circuit 37.

[0078] In this arrangement, the delay element 44 can delay one of a pairof differential signals input to the gates of the differential inputMOSFETs 32 and 33, and compensate for the signal delay time generated bythe line length difference between a pair of differential lines SA andSB, reducing a skew and common mode noise.

[0079]FIGS. 8A and 8B show simulation results when the delay element 44is inserted on the input stage of the differential output driver circuit31. The frequency of a pair of differential signals is 4.0 GHz, theelectrical lengths (wiring lengths) of the signal lines SA and SB for apair of differential signals are 298 mm and 302 mm, respectively, andthe input and output are terminated at 50Ω. FIG. 8A shows, as thesimulation results of common mode noise, the peak-to-peak value of thecommon mode component of a pair of differential signals (added waveformof a pair of differential signals). FIG. 8B shows, as the simulationresults of a differential mode, the maximum value of the waveforms of apair of differential signals. FIG. 8C shows transition of the waveformsof a pair of differential signals. When signals which propagate throughthe signal lines SA and SB for a pair of differential signals are “. . .010 . . .” and “. . . 101 . . .”, a peak-to-peak value ΔV in the commonmode in FIG. 8A represents the absolute value of the difference betweencommon mode components at intersections N1 and N2 in transition of apair of differential signals, as shown in FIG. 8C. The peak-to-peakvalue ΔV increases depending on the electrical length difference betweenthe signal lines SA and SB.

[0080] In FIGS. 8A and 8B, (A) shows a value in the second embodiment ofthe present invention (the delay element 44 having a delay element of 60psec is arranged). (B) shows a value in the prior art using no delayelement, and (C) shows a value when both the signal lines SA and SB fora pair of differential signals have the same electrical length of 300mm. As is apparent from FIG. 8B, the signal component is smaller by 2.4%in (A) than those in (B) and (C). However, the common mode component in(A) is smaller by 15% than that in (B), as shown in FIG. 8A, and comesclose to an ideal value in (C), realizing reduction in common modenoise.

EXAMPLE 5

[0081]FIG. 9 shows a concrete implementation example of the delayelement 44 in the semiconductor integrated circuit device according tothe second embodiment. In FIG. 9, the same reference numerals as in FIG.7 denote the same parts, and a detailed description thereof will beomitted.

[0082] In this example, a capacitance element 44A formed from the gatecapacitance of an active element is arranged as the delay element 44shown in FIG. 7.

[0083] For example, in a MOS capacitor, a very thin oxide film serves asa capacitor dielectric, and the line length difference (delay timedifference) between a pair of differential lines (signal lines SA andSB) can be compensated for by a very small pattern occupation area. TheMOS capacitor can be formed simultaneously in the step of forming thedifferential input MOSFETs 32 and 33. No new manufacturing step need beadded for forming the delay element 44.

[0084] In this arrangement, the delay of one of a pair of differentialsignals that is supplied to the MOSFET 33 can be increased to set alarge signal delay amount of a shorter one (in this case, the signalline SA) of a pair of differential lines. The signal delay time by theline length difference between the signal lines SA and SB can becompensated for, reducing a skew and common mode noise.

EXAMPLE 6

[0085]FIG. 10 shows another concrete implementation example of the delayelement 44 in the semiconductor integrated circuit device according tothe second embodiment. In FIG. 10, the same reference numerals as inFIG. 7 denote the same parts, and a detailed description thereof will beomitted.

[0086] In this example, a control circuit 45A and a plurality of (n)capacitance elements (e.g., MOS capacitors) 44A-1, . . . , 44A-n eachformed from the gate capacitance of an active element are arranged asthe delay element 44 shown in FIG. 7. The control circuit 45A isinterposed between one electrode of each of the capacitance elements44A-1, . . . , 44A-n and the gate of the MOSFET 33. The control circuit45A controls a potential applied to one electrode of each of thecapacitance elements 44A-1, . . . , 44A-n, selectively changing thethickness of the depletion layer of each capacitance element. Thecapacitance connected to the gate of the MOSFET 33 can be changed tofreely set the signal delay amount.

[0087] This arrangement can finely control the signal delay amount byusing the control circuit 45A, in addition to the effects of Example 5.

[0088] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

[0089] The capacitance ratio of the n capacitance elements 44A-1, . . ., 44A-n is set to 1:2:4: . . . :2^(n) so as to change the delay amountat a 2^(n)-power step. By selecting the capacitance elements 44A-1, . .. , 44A-n, the delay amount can be set at a fine step within a widerange of a large capacity to a small capacity, and can be moreaccurately controlled.

EXAMPLE 7

[0090]FIG. 11 shows still another concrete implementation example of thedelay element 44 in the semiconductor integrated circuit deviceaccording to the second embodiment. In FIG. 11, the same referencenumerals as in FIG. 7 denote the same parts, and a detailed descriptionthereof will be omitted.

[0091] In this example, the current path of each of switching elements(MOSFETs) 46-1, . . . , 46-n is connected between one electrode (gateelectrode) of a corresponding one of capacitance elements 44A-1, . . . ,44A-n and the gate of the MOSFET 33. A control circuit 45B selectivelyapplies a high-level (“H”-level) or low-level (“L”-level) potential tothe gates of the MOSFETs 46-1, . . . , 46-n, and controls their ON/OFFoperation.

[0092] Which gate capacitance (capacitance element 44A-1, . . . , 44A-n)is to be connected to the MOSFET 33 can be selected, and the signaldelay amount can be freely controlled.

[0093] The capacitance ratio of the n capacitance elements 44A-1, . . ., 44A-n is set to 1:2:4: . . . :2^(n) so as to change the delay amountat a 2^(n)-power step. By selecting the capacitance elements 44A-1, . .. , 44A-n, the delay amount can be set at a fine step within a widerange of a large capacity to a small capacity, and can be moreaccurately controlled.

[0094] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

EXAMPLE 8

[0095]FIG. 12 shows still another concrete implementation example of thedelay element 44 in the semiconductor integrated circuit deviceaccording to the second embodiment. In FIG. 12, the same referencenumerals as in FIG. 7 denote the same parts, and a detailed descriptionthereof will be omitted.

[0096] In this example, one electrode (gate electrode) of each ofcapacitance elements 44A-1, . . . , 44-n is connected to the gate of theMOSFET 33. A control circuit 45C selectively applies an “H”- or“L”-level potential to the other electrode (layer which forms a counterelectrode with respect to the gate electrode) of each of the capacitanceelements 44A-1, . . . , 44A-n.

[0097] The capacitances of the capacitance elements 44A-1, . . . , 44A-nconnected to the gate of the MOSFET 33 can be selected, freelycontrolling the signal delay amount.

[0098] In Example 8, similar to Example 3, the capacitance ratio of then capacitance elements is set to 1:2:4: . . . :2^(n) so as to change thedelay amount at a 2^(n)-power step. By selecting the capacitanceelements 44A-1, . . . , 44A-n, the delay amount can be set at a finestep within a wide range of a large capacity to a small capacity, andcan be more accurately controlled.

[0099] The signal delay time by the line length difference between apair of differential lines can be more accurately compensated for, and askew and common mode noise can be further reduced.

[0100] In the second embodiment and Examples 5 to 8, the delay element44 is inserted in one of the signal lines SC and SD which transmit apair of differential signals from the circuit 37 to the differentialoutput driver circuit 31 so as to adjust the delays of signals passingthrough the signal lines SA and SB to be substantially equal to eachother. It is also possible to arrange the delay elements 44 on both thesignal lines SC and SD and adjust signal delay times generated by theline length difference between a pair of differential lines SA and SB soas to be substantially equal to each other.

[0101] A plurality of delay elements having different structures may becombined and inserted in at least one of the signal lines SA and SBwhich transmit a pair of differential signals to the gates of thedifferential input MOSFETs 32 and 33.

EXAMPLE 9

[0102]FIG. 13 shows still another concrete implementation example of thedelay element 44 in the semiconductor integrated circuit deviceaccording to the third embodiment. In FIG. 13, the same referencenumerals as in FIG. 7 denote the same parts, and a detailed descriptionthereof will be omitted.

[0103] In Example 9, flip-flop circuits 47 and 48 are inserted in thesignal lines SC and SD which transmit a pair of differential signalsfrom the circuit 37 to the differential output driver circuit 31. Acontrol circuit 45D supplies clock signals in different phases to theflip-flop circuits 47 and 48.

[0104] The control circuit 45D supplies clock signals in differentphases to the flip-flop circuits 47 and 48 to control them. A pair ofdifferential signals can be synchronized at different timings, and thedelay amount between a pair of differential signals can be so controlledas to adjust the delays of signals passing through the signal lines SAand SB to be substantially equal to each other.

[0105] Note the clock signals supplied to the flip-flop circuits 47 and48 can be use of in-phase signals.

[0106] According to the arrangement of Example 9, the delay amount canbe freely controlled without degrading the rise/fall times of a pair ofdifferential signals. The signal delay time by the line lengthdifference between a pair of differential lines (signal lines SA and SB)can be accurately compensated for without degrading the rise/fall timesof a pair of differential signals, and a skew and common mode noise canbe further reduced.

THIRD EMBODIMENT

[0107]FIG. 14 is a circuit diagram for explaining a semiconductorintegrated circuit device according to the third embodiment of thepresent invention. A plurality of (m) differential output drivercircuits 51-1, . . . , 51-m described in Example 9, and an I/O circuit52 having no terminal resistor on the receiving side are formed on asemiconductor chip 50.

[0108] The chip 50 is mounted on a printed circuit board 53.Transmission lines 42 and 43 on the printed circuit board 53 areconnected to the differential output driver circuit 51-1 via bumps 40and 41. A transmission line 54 on the printed circuit board 53 isconnected to the I/O circuit 52 via a bump 55.

[0109] The I/O circuit 52 comprises a CMOS inverter 63 formed from aP-channel MOSFET 61 and N-channel MOSFET 62, and a CMOS inverter 66formed from a P-channel MOSFET 64 and N-channel MOSFET 65. The CMOSinverter 63 is used as an output, its input terminal is connected to aninternal circuit, and its output terminal is connected to one end of aglobal interconnection 67. The CMOS inverter 66 is used as an input, itsinput terminal is connected to one end of the global interconnection 67,and its output terminal is connected to the internal circuit. The otherend of the global interconnection 67 is connected to the bump 55, andthe bump 55 is connected to the transmission line 54 on the printedcircuit board 53.

[0110] That is, in the third embodiment, the I/O circuit 52 having noterminal resistor on the receiving side is integrated in one chip 50having many differential output driver circuits.

[0111] The I/O circuit 52 having no terminal resistor on the receivingside is generally used for a low-speed signal. When the transmissionline 54 used by the I/O circuit 52 is formed on the same printed circuitboard 53 as the transmission lines 42 and 43 used by the differentialoutput driver circuits 51-1, . . . , 51-m, the transmission line 54having no termination is readily coupled to common mode noise, and thecommon mode noise component is radiated from the transmission line 54.

[0112] Even in the presence of both the high-speed I/O circuit andlow-speed I/O circuit, the radiation level of electromagnetic waves fromthe transmission line connected to the low-speed I/O circuit can bereduced by reducing a skew and common mode noise in the differentialoutput driver circuits 51-1, . . . , 51-m.

[0113] The control circuits 45D in the differential output drivercircuits 51-1, . . . , 51-m are controlled to control the delay timebetween the m driver circuits 51-1, . . . , 51-m and the I/O circuit 52in consideration of a skew and common mode noise. This enablesadjustment considering the entire chip.

[0114]FIG. 14 illustrates the differential output driver circuits 51-1,. . . , 51-m having the arrangement shown in FIG. 13. The circuit in anyone of the embodiments or examples can be similarly applied. A TTLinterface has been described as an example of an I/O circuit having noterminal resistor on the receiving side, but an I/O circuit of anothertype can be adopted.

FOURTH EMBODIMENT

[0115]FIG. 15 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals and itsperipheral circuit, in order to explain a system using a semiconductorintegrated circuit device according to the fourth embodiment of thepresent invention.

[0116] In the fourth embodiment, a receiving circuit 68, signalselecting circuit 69, and switching signal generator 70 are formedwithin a chip (semiconductor integrated circuit device). The receivingcircuit 68 receives correction data having passed through globalinterconnections 38 and 39 outside the chip, and supplies the data tothe signal selecting circuit 69. The receiving circuit 68 incorporates asignal processing circuit which generates a control signal. The signalselecting circuit 69 is controlled by a switching signal SW output fromthe switching signal generator 70. The signal selecting circuit 69switches between a control signal output from the receiving circuit 68and a control signal CS supplied from the internal circuit or outsidethe chip, and supplies the selected signal to a control circuit 45E.

[0117] A receiving circuit 71, transmitting circuit 72, and signalprocessing device 73 are arranged outside the chip. The receivingcircuit 71 receives a pair of differential signals output from thesemiconductor integrated circuit device via signal lines SA and SB. Thesignal processing device 73 processes the pair of differential signalsreceived by the receiving circuit 71, and generates correction data forcorrecting unbalance between the pair of differential signals. Thetransmitting circuit 72 transmits the correction data generated by thesignal processing apparatus 73 to the semiconductor integrated circuitdevice. The transmitting circuit 72 is mounted on the same chip as thatof the receiving circuit 71.

[0118] In this arrangement, the receiving circuit 71 monitors a pair ofdifferential signals output from the semiconductor integrated circuitdevice, and the signal processing device 73 obtains a delay amount so asto attain an optimal reception signal waveform. Correction data as aprocessing result obtained by the signal processing device 73 issupplied from the transmitting circuit 72 to the receiving circuit 68via transmission lines 42 and 43, pads 40 and 41, and globalinterconnections 38 and 39. The signal processing circuit in thereceiving circuit 68 generates a control signal for controlling thecontrol circuit 45E. Under the control of the switching signal generator70, the signal selecting circuit 69 supplies a control signal generatedby the signal processing circuit or the control signal CS to the controlcircuit 45E. Flip-flop circuits 47 and 48 are controlled, and a pair ofdifferential signals supplied from a circuit 37 on the input stage tothe gates of differential input MOSFETs 32 and 33 are synchronized witheach other.

[0119] The system having this arrangement monitors a pair ofdifferential signals output from the semiconductor integrated circuitdevice, determines a delay amount, and can optimize the delay amount. Inaddition, the waveforms of a pair of differential signals output fromthe semiconductor integrated circuit device can be optimized. A skew andcommon mode noise generated by the line length difference between a pairof differential lines connected to the semiconductor integrated circuitdevice can be more effectively reduced.

[0120] The fourth embodiment has exemplified an arrangement using theflip-flop circuits 47 and 48 shown in FIG. 13. The structure in any oneof the embodiments or examples can be similarly applied.

[0121] Correction data output from the transmitting circuit 72 issupplied to the receiving circuit 68 by using the signal lines SA and SBfor externally outputting a pair of differential signals. Correctiondata may be input to the receiving circuit 68 via another path.

FIFTH EMBODIMENT

[0122]FIG. 16 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals and itsperipheral circuit, in order to explain a semiconductor integratedcircuit device and a system using the semiconductor integrated circuitdevice according to the fifth embodiment of the present invention. Inthe fifth embodiment, a test signal generating circuit 74 is arranged ona chip, and a control circuit 45F is controlled by a signal output fromthe test signal generating circuit 74.

[0123] The test signal generating circuit 74 changes the phase of aclock signal output from the control circuit 45F, and controls the delayamounts of a pair of differential signals by flip-flop circuits 47 and48. An IC tester is connected to transmission lines 42 and 43 todetermine the difference between a pair of differential signals andcheck a margin for the delay amount. At this time, a test signal TS issupplied from the IC tester to the test signal generating circuit 74,controlling the operation.

[0124] Since the test signal generating circuit 74 is incorporated inthe chip, a margin for a skew or common mode noise generated byunbalance between a pair of differential signals can be tested.

[0125] The fifth embodiment has exemplified an arrangement using theflip-flop circuits 47 and 48 shown in FIG. 13. The test signalgenerating circuit 74 may be similarly arranged in the structure in anyone of the embodiments or examples.

SIXTH EMBODIMENT

[0126]FIG. 17 shows an output circuit (differential output drivercircuit) which transmits a pair of differential signals and itsperipheral circuit, in order to explain a semiconductor integratedcircuit device and a system using the semiconductor integrated circuitdevice according to the sixth embodiment of the present invention. Thesixth embodiment adopts a combination of the arrangement according tothe fourth embodiment and the arrangement according to the fifthembodiment.

[0127] The circuit shown in FIG. 17 has the functions of both thecontrol circuit 45E shown in FIG. 15 and the control circuit 45F shownin FIG. 16. The remaining arrangement is the same as those of thecircuits shown in FIGS. 15 and 16. The same reference numerals denotethe same parts, and a detailed description thereof will be omitted.

[0128] In this arrangement, a pair of differential signals output fromthe semiconductor integrated circuit device upon reception of a testsignal are monitored by a receiving circuit 71. Flip-flop circuits 47and 48 are controlled in accordance with the monitoring result, and thepair of differential signals can be synchronized at different timings.Hence, the effects of both the circuits shown in FIGS. 15 and 16 can beobtained.

[0129] As has been described above, the semiconductor integrated circuitdevice according to the first to sixth embodiments of the presentinvention can suppress a skew and common mode noise generated by theline length difference between a pair of differential lines.

[0130] The system using the semiconductor integrated circuit deviceaccording to the fourth to sixth embodiments of the present inventioncan optimize the waveforms of a pair of differential signals.

[0131] The system using the semiconductor integrated circuit deviceaccording to the fifth and sixth embodiments of the present inventioncan check a margin for a skew or common mode noise generated byunbalance between a pair of differential signals owing to manufacturingvariations.

[0132] As described above, according to one aspect of this invention,there is provided a semiconductor integrated circuit device capable ofsuppressing a skew and common mode noise generated by the line lengthdifference between a pair of differential lines.

[0133] Also, there is provided a system using a semiconductor integratedcircuit device that can check a margin for a skew or common mode noisegenerated by manufacturing variations.

[0134] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

1-35. (Canceled)
 36. A semiconductor integrated circuit devicecomprising: a chip on which an integrated circuit is formed; adifferential output driver circuit which externally outputs a pair ofdifferential signals generated by the integrated circuit; first andsecond signal lines which transmit the pair of differential signalsoutput from the differential output driver circuit; third and fourthsignal lines which transmit the pair of differential signals from theintegrated circuit to the differential output driver circuit; and adelay unit which is connected in the chip to at least one of the thirdand fourth signal lines, has an active element for delaying at least oneof the pair of differential signals so as to make delays of the signalspassing through the first and second signal lines substantially equal toeach other, and compensates for a signal delay time generated by a linelength difference between the first and second signal lines.
 37. Thedevice according to claim 36, wherein the delay unit includes acapacitance element having one electrode connected to a signal line witha shorter line length out of the first and second signal lines on thethird and fourth signal lines, and the capacitance element includes acapacitance element using a MOS (Metal-Oxide-Semiconductor) gatecapacitance.
 38. The device according to claim 36, wherein the delayunit can change a delay time.
 39. The device according to claim 38,wherein the delay unit comprises a plurality of capacitance elements,and a control circuit which is interposed between a signal line with ashorter line length out of the first and second signal lines on thethird and fourth signal lines and one electrode of each of saidplurality of capacitance elements and selectively applies a potential tosaid one electrode of each of said plurality of capacitance elements.40. The device according to claim 38, wherein the delay unit comprises aplurality of capacitance elements, a plurality of switching elementseach of which is connected between one electrode of a corresponding oneof said plurality of capacitance elements and a signal line with ashorter line length out of the first and second signal lines on thethird and fourth signal lines, and a control circuit which selectivelyON/OFF-controls said plurality of switching elements.
 41. The deviceaccording to claim 38, wherein the delay unit comprises a plurality ofcapacitance elements each having one electrode connected to a signalline with a shorter line length out of the first and second signal lineson the third and fourth signal lines, and a control circuit whichselectively applies a potential to the other electrode of each of saidplurality of capacitance elements.
 42. The device according to claim 38,wherein the delay unit comprises first and second flip-flop circuitswhich receive the pair of differential signals having passed through thethird and fourth signal lines from the integrated circuit, and a controlcircuit which supplies clock signals to the first and second flip-flopcircuits.
 43. The device according to claim 36, further comprising aninput/output circuit which is arranged in the chip and has at least oneof an input and output not terminated with impedance matching.
 44. Thedevice according to claim 36, in which the delay unit comprises acontrol circuit that controls a delay time, and which further comprisesa receiving circuit that is arranged in the chip and receives correctiondata having passed through the first and second signal lines, a signalselecting circuit which receives an output signal from the receivingcircuit and a control signal and supplies a selected signal to thecontrol circuit, and a switching signal generator which supplies aswitching signal to the signal selecting circuit.
 45. The deviceaccording to claim 36, in which the delay unit comprises a controlcircuit that controls a delay time, and which further comprises a testunit that controls the control circuit and checks a margin for unbalancebetween the pair of differential signals.
 46. The device according toclaim 45, wherein the test unit includes a test signal generationcircuit which is arranged in the chip, generates a test signal, andsupplies the test signal to the control circuit.
 47. The deviceaccording to claim 45, wherein the test unit includes a tester which isconnected to the first and second signal lines, determines a differencebetween the pair of differential signals, and checks a margin for adelay amount.
 48. A system using a semiconductor integrated circuitdevice, comprising: a semiconductor integrated circuit device comprisinga differential output driver circuit which externally outputs via firstand second signal lines a pair of differential signals generated withina chip; a first receiving unit which receives the pair of differentialsignals output from the semiconductor integrated circuit device via thefirst and second signal lines; a signal processing unit which processesthe pair of differential signals received by the first receiving unitand generates correction data for correcting unbalance between the pairof differential signals; a transmitting unit which transmits thecorrection data generated by the signal processing unit to thesemiconductor integrated circuit device; a second receiving unit whichis arranged in the semiconductor integrated circuit device and receivesthe correction data transmitted from the transmitting unit; and a delayunit which changes a delay time on the basis of the correction datareceived by the second receiving unit, has an active element fordelaying signals passing through the first and second signal lines so asto make delays of the signals substantially equal to each other, andcompensates for a signal delay time generated by a line lengthdifference between the first and second signal lines.
 49. The systemaccording to claim 48, further comprising a test unit which controls thedelay unit and checks a margin for unbalance between the pair ofdifferential signals.
 50. The system according to claim 49, wherein thetest unit includes a test signal generation circuit which is arranged inthe chip, generates a test signal, and supplies the test signal to thedelay unit.
 51. The system according to claim 50, wherein the test unitincludes a tester which is connected to the first and second signallines, determines a difference between the pair of differential signals,and checks a margin for a delay amount.
 52. The system according toclaim 48, wherein the delay unit is inserted in at least one of thefirst and second signal lines.
 53. The system according to claim 52,wherein the delay unit is inserted in at least one of third and fourthsignal lines in an internal circuit which supplies the pair ofdifferential signals to the differential output driver circuit.
 54. Thesystem according to claim 48, wherein the delay unit comprises first andsecond flip-flop circuits, and a control circuit which supplies clocksignals in different phases to the first and second flip-flop circuits,and the control circuit is controlled on the basis of the correctiondata received by the second receiving unit.
 55. The system according toclaim 54, wherein the second receiving unit comprises a receivingcircuit which receives the correction data output from the transmittingunit, a signal selecting circuit which receives the correction datareceived by the receiving circuit and a control signal, selects one ofthe correction data and the control signal, and supplies a selectedsignal to the control circuit, and a switching signal generator whichsupplies a switching signal to the signal selecting circuit and controlsselection.
 56. The system according to claim 55, wherein the receivingcircuit receives the correction data which is output from thetransmitting unit and transmitted through the first and second signallines.
 57. The system according to claim 48, wherein the delay unitcomprises a plurality of capacitance elements, and a control circuitwhich selects said plurality of capacitance elements and controls thedelay time, and the control circuit is controlled on the basis of thecorrection data received by the second receiving unit.
 58. The systemaccording to claim 57, wherein the second receiving unit comprises areceiving circuit which receives the correction data output from thetransmitting unit, a signal selecting circuit which receives thecorrection data received by the receiving circuit and a control signal,selects one of the correction data and the control signal, and suppliesa selected signal to the control circuit, and a switching signalgenerator which supplies a switching signal to the signal selectingcircuit and controls selection.
 59. The system according to claim 58,wherein the receiving circuit receives the correction data which isoutput from the transmitting unit and transmitted through the first andsecond signal lines.
 60. A semiconductor integrated circuit devicecomprising: a chip on which an integrated circuit is formed; adifferential output driver circuit which externally outputs a pair ofdifferential signals generated by the integrated circuit; first andsecond signal lines which transmit the pair of differential signalsoutput from the differential output driver circuit; a delay unit whichis connected in the chip to at least one of the first and second signallines, has an active element for delaying signals passing through thefirst and second signal lines so as to make delays of the signalssubstantially equal to each other, and compensates for a signal delaytime generated by a line length difference between the first and secondsignal lines; and an input/output circuit which is arranged in the chipand has at least one of an input and output not terminated withimpedance matching.
 61. A semiconductor integrated circuit devicecomprising: a chip on which an integrated circuit is formed; adifferential output driver circuit which externally outputs a pair ofdifferential signals generated by the integrated circuit; first andsecond signal lines which transmit the pair of differential signalsoutput from the differential output driver circuit; and a delay unitwhich is connected in the chip to at least one of the first and secondsignal lines, has an active element for delaying signals passing throughthe first and second signal lines so as to make delays of the signalssubstantially equal to each other, and compensates for a signal delaytime generated by a line length difference between the first and secondsignal lines, the delay unit comprising a control circuit that controlsa delay time; and a receiving circuit that is arranged in the chip andreceives correction data having passed through the first and secondsignal lines, a signal selecting circuit which receives an output signalfrom the receiving circuit and a control signal and supplies a selectedsignal to the control circuit, and a switching signal generator whichsupplies a switching signal to the signal selecting circuit.
 62. Asemiconductor integrated circuit device comprising: a chip on which anintegrated circuit is formed; a differential output driver circuit whichexternally outputs a pair of differential signals generated by theintegrated circuit; first and second signal lines which transmit thepair of differential signals output from the differential output drivercircuit; and a delay unit which is connected in the chip to at least oneof the first and second signal lines, has an active element for delayingsignals passing through the first and second signal lines so as to makedelays of the signals substantially equal to each other, and compensatesfor a signal delay time generated by a line length difference betweenthe first and second signal lines, the delay unit comprising a controlcircuit that controls a delay time; and a test unit that controls thecontrol circuit and checks a margin for unbalance between the pair ofdifferential signals.
 63. The device according to claim 62, wherein thetest unit includes a test signal generation circuit which is arranged inthe chip, generates a test signal, and supplies the test signal to thecontrol circuit.
 64. The device according to claim 62, wherein the testunit includes a tester which is connected to the first and second signallines, determines a difference between the pair of differential signals,and checks a margin for a delay amount.